Sigma-Delta Modulator Oversampling Ratio Calculator
Find a sigma-delta ADC's oversampling ratio, SQNR, and effective number of bits.
🔁 What is Sigma-Delta Modulator Oversampling Ratio?
Sigma-delta (delta-sigma) oversampling ratio describes how many times faster a sigma-delta ADC samples a signal compared to the Nyquist minimum needed to capture it, and it is the single biggest lever a designer has for trading sampling speed against resolution. Instead of using a high-resolution quantizer at the signal's Nyquist rate like a conventional ADC, a sigma-delta converter runs a coarse (often 1-bit) quantizer at a much higher rate inside a feedback loop that pushes quantization noise out of the signal band, then relies on oversampling and digital filtering to recover high effective resolution.
Audio codec designers use this trade-off to build 16 to 24-bit effective converters from a 1-bit modulator running at megahertz rates. Precision instrumentation and industrial measurement ADCs use very high OSR sigma-delta converters to reach 20+ bits of resolution at slow output rates for weigh scales, thermocouples, and strain gauges. Wireless baseband and RF sampling designs use sigma-delta ADCs and DACs specifically because the oversampling ratio can be tuned against modulator order to hit a target dynamic range without needing an impractically precise multi-bit quantizer.
A common misconception is that oversampling alone is what improves resolution. Plain oversampling without noise shaping (no feedback loop) only gives 3 dB (half a bit) per doubling of OSR, the same as simple averaging. The sigma-delta feedback loop is what shapes quantization noise away from the signal band, so that oversampling delivers (20L+10) dB per decade for an L-th order loop, dramatically more than plain averaging alone.
This calculator computes OSR from your bandwidth and sampling rate, then applies the standard idealized SQNR formula for your chosen modulator order and quantizer bit depth, converting the result into effective number of bits (ENOB) for direct comparison against conventional ADCs.
📐 Formula
📖 How to Use This Calculator
Steps
💡 Example Calculations
Example 1 — Audio-Rate Second-Order 1-Bit Modulator
fB = 20,000 Hz, fs = 2,560,000 Hz, B = 1 bit, L = 2
Example 2 — First-Order Modulator Needs Higher OSR
fB = 25,000 Hz, fs = 6,400,000 Hz, B = 1 bit, L = 1
Example 3 — High-Resolution Instrumentation ADC
fB = 8,000 Hz, fs = 3,072,000 Hz, B = 2 bits, L = 3
❓ Frequently Asked Questions
🔗 Related Calculators
What is the oversampling ratio in a sigma-delta ADC?
The oversampling ratio (OSR) is how many times faster a sigma-delta modulator samples a signal compared to the Nyquist minimum, OSR = fs / (2 x fB), where fs is the sampling rate and fB is the signal bandwidth. A CD-quality audio signal (fB = 20 kHz) sampled at 2.56 MHz has an OSR of 64.
How does oversampling ratio affect SQNR?
SQNR increases by (20L+10) dB for every decade increase in OSR, where L is the modulator order, so a first-order modulator gains about 9 dB per octave of OSR while a second-order modulator gains about 15 dB per octave. Higher OSR always improves SQNR, but higher-order modulators extract more benefit from the same oversampling.
What is the SQNR formula for a sigma-delta modulator?
SQNR (dB) = 6.02B + 1.76 + 10*log10((2L+1)/pi^(2L)) + (20L+10)*log10(OSR), where B is the quantizer bit depth, L is the modulator order, and OSR is the oversampling ratio. The first two terms are the standard ideal-ADC SQNR formula; the remaining terms capture the noise-shaping benefit of the sigma-delta loop.
What does modulator order mean?
Modulator order (L) is the number of integrator stages in the sigma-delta feedback loop. Each additional order pushes quantization noise further out of the signal band (steeper high-pass noise shaping), at the cost of a more complex loop that is harder to keep stable, which is why most designs use order 1 through 4.
How do I convert SQNR into effective number of bits (ENOB)?
ENOB = (SQNR - 1.76) / 6.02, the same conversion used for any ADC's SINAD-to-ENOB relationship. It expresses the converter's real dynamic range as an equivalent ideal bit depth, useful for comparing oversampled converters against conventional Nyquist-rate ADCs.
Why do most sigma-delta ADCs use only a 1-bit quantizer?
A 1-bit (2-level) quantizer is inherently linear (only two output codes, so no differential nonlinearity is possible) and simplifies the feedback DAC to two reference voltages with no matching error. The formula still applies with B = 1; the SQNR then comes almost entirely from oversampling and noise shaping rather than quantizer resolution.
Why does a first-order modulator need such a high OSR?
A first-order loop shapes noise with only a single differentiator (20 dB/decade slope past the signal band), so it needs a large OSR to push enough of that noise beyond the signal bandwidth. Second and third-order loops shape noise more steeply (40 and 60 dB/decade), reaching the same SQNR at a much lower OSR, which is why almost no commercial sigma-delta ADC uses first order alone.
Is there a practical limit to how high OSR or modulator order can go?
Yes. Raising OSR costs clock speed and power, since the modulator must run at fs = 2 x fB x OSR regardless of the final output data rate. Raising modulator order beyond 3rd to 5th order risks loop instability and limit cycles unless carefully compensated, so real designs balance order and OSR rather than maximizing either alone.
How does this relate to the decimation filter after the modulator?
The sigma-delta modulator's 1-bit (or few-bit) high-rate output still needs a digital decimation filter to remove out-of-band shaped noise and reduce the data rate back down to roughly 2 x fB, recovering the full SQNR predicted here as usable resolution in the final multi-bit output word. See the Decimation and Interpolation Factor Calculator for that filtering stage.
How accurate is the ideal SQNR formula compared to a real chip's datasheet SNR?
The formula gives the theoretical ceiling assuming perfect integrators, no thermal noise, and no idle tones or limit cycles; real sigma-delta ADCs typically fall 5 to 15 dB short of this ideal figure due to circuit noise, nonlinearity, and clock jitter, so treat this calculator's output as a best-case upper bound for architecture comparison, not a datasheet prediction.