Phase Noise and Jitter Calculator
Convert an oscillator or clock's phase noise spec into RMS phase jitter and RMS time jitter.
📻 What is Phase Noise and Jitter?
Phase noise and jitter both describe the same fundamental imperfection in a real oscillator or clock: instead of ticking with perfectly regular timing, every real clock's edges wander slightly from their ideal positions due to random phase fluctuations. Phase noise measures this wander in the frequency domain (dBc/Hz at a given offset from the carrier), while jitter measures it directly in the time domain (seconds of timing error), and the two are directly convertible into each other.
RF and wireless engineers specify phase noise on local oscillators (LOs) because it directly sets a receiver's ability to reject a strong nearby interferer (reciprocal mixing) and a transmitter's spectral purity. High-speed ADC and DAC designers convert clock phase noise into jitter because sampling clock jitter directly caps the achievable signal-to-noise ratio at high input frequencies, no matter how good the converter itself is. Digital communications and networking engineers track jitter budgets across clock distribution trees to keep bit-error rates under control in high-speed serial links.
A common misconception is that phase noise and jitter are two unrelated specifications that both happen to matter for oscillators. They are not separate quantities, jitter is simply the time-domain integral of phase noise, converted through the oscillator's own carrier frequency. Two oscillators with the same phase noise level but different carrier frequencies have different jitter, since jitter also depends on how fast the carrier itself is cycling.
This calculator applies the standard spot-noise approximation used throughout the ADC and clock industry to convert a phase noise specification directly into RMS phase jitter and RMS time jitter.
📐 Formula
📖 How to Use This Calculator
Steps
💡 Example Calculations
Example 1 — ADC Sampling Clock Jitter Budget
L = -100 dBc/Hz, BW = 1,000,000 Hz, fc = 100,000,000 Hz
Example 2 — RF Local Oscillator Jitter
L = -120 dBc/Hz, BW = 10,000,000 Hz, fc = 10,000,000 Hz
Example 3 — Low-Jitter High-Speed Clock
L = -140 dBc/Hz, BW = 1,000,000,000 Hz, fc = 1,000,000,000 Hz
❓ Frequently Asked Questions
🔗 Related Calculators
What is phase noise?
Phase noise measures how much an oscillator's instantaneous phase (and therefore frequency) randomly fluctuates around its ideal value, expressed in dBc/Hz (decibels relative to the carrier, per Hz of measurement bandwidth) at a specified offset frequency from the carrier.
What is jitter and how does it relate to phase noise?
Jitter is the time-domain expression of the same phase instability that phase noise describes in the frequency domain, the random deviation of a clock edge's actual timing from its ideal periodic position. Integrating an oscillator's phase noise over a bandwidth and converting the result to a time value produces an RMS jitter figure.
How do you convert phase noise to jitter?
The standard spot-noise formula is t_rms = sqrt(2 * 10^(L/10) * BW) / (2*pi*fc), where L is the phase noise level in dBc/Hz, BW is the integration bandwidth in Hz, and fc is the carrier frequency in Hz. This treats the phase noise as roughly constant (flat) across the integration bandwidth, a standard simplifying approximation.
Why does the formula include a factor of 2?
Phase noise specifications are typically single-sideband (SSB) values, describing only the noise on one side of the carrier. The factor of 2 accounts for the mirror-image noise power on the other sideband, which also contributes to the total phase fluctuation being converted into a jitter figure.
Why does jitter decrease as carrier frequency increases (for the same phase noise)?
The conversion divides phase jitter (in radians) by 2*pi*fc to get time jitter. A given amount of phase error corresponds to a smaller absolute time error when the carrier's period is shorter (higher frequency), since the same phase fraction of a cycle now spans less real time.
Is this the exact way jitter is computed from a real phase noise plot?
No, this uses the simplified spot-noise (flat-phase-noise) approximation common on datasheets and quick estimation tools. A rigorous jitter calculation integrates the actual measured phase noise curve, which typically varies significantly across frequency offset, over the desired bandwidth using numerical integration rather than treating it as constant.
How does clock jitter affect ADC performance?
Sampling clock jitter directly limits an ADC's achievable SNR at high input frequencies, following SNR_jitter = -20*log10(2*pi*f_in*t_jitter). A 1 GHz input signal sampled with even 1 ps of RMS clock jitter caps SNR at roughly 44 dB, regardless of how good the ADC itself is, which is why high-speed ADC systems demand extremely low-jitter clock sources.
What is a typical phase noise spec for a good crystal oscillator?
A high-quality OCXO (oven-controlled crystal oscillator) might specify phase noise around -140 to -160 dBc/Hz at a 10 kHz offset, while a lower-cost XO might be -90 to -110 dBc/Hz at the same offset, roughly 50 dB (a factor of about 300 in jitter) apart.
Does a larger integration bandwidth always mean more jitter?
Yes, for a fixed (flat) phase noise level, integrating over a wider bandwidth accumulates more total noise power, increasing the resulting RMS jitter proportional to the square root of the bandwidth. This is why jitter specifications always state the integration bandwidth alongside the number itself, the same jitter figure without a bandwidth is not directly comparable across datasheets.
Can I convert time jitter back into an equivalent phase noise level?
Yes, algebraically: solving the same formula for L gives L = 10*log10(t_rms^2 * (2*pi*fc)^2 / (2*BW)). This calculator computes forward (phase noise to jitter), but the same relationship works in reverse if you already know a jitter spec and want an equivalent flat phase noise figure for comparison.